A large scale integrated (LSI) circuit used in a microcomputer for a digital appliance, a personal computer, or the like, or an analog high-frequency electronic part (for example, a transmitting amplifier, an integrated circuit for signal reception, or the like) used in a mobile communication terminal is required to achieve high performance such as high speed, low power consumption, multifunction, or cost reduction. In an electronic element configuring the integrated circuit, for example, a silicon (Si) field-effect transistor (also called FET), high performance of the element (improvement of current driving force and reduction of power consumption) has been realized by fully using photolithography technique to mainly shorten the gate length.
However, in a MIS (Metal Insulator Semiconductor) type field-effect transistor (hereinafter, simply called MIS transistor) having a gate length of 100 nm or shorter, the performance improvement rate is saturated (or reduced). This is mainly caused by increase of gate leakage current due to thinning of a gate insulating film and limitation in reduction of the equivalent oxide thickness (EOT) due to depletion of a polycrystalline silicon (also called polysilicon) gate electrode. In order to solve the issues, there is a technique for achieving the performance improvement of the MIS transistor by replacing a silicon oxide (SiO2) gate insulating film by a high-dielectric (high-K) gate insulating film and replacing the polysilicon gate electrode by a metal gate electrode.
By employing the high-K gate insulating film and the metal gate electrode to a gate, a physical film thickness of the gate insulating film for obtaining the same equivalent oxide film thickness as the silicon oxide film can be made thick. Thereby, the gate leakage current can be reduced and the gate depletion can be suppressed, so that the driving current can be improved. However, heat resistance of materials configuring these high-K gate insulating film and the metal gate electrode is lower than that of silicon oxide and polysilicon. Therefore, phase change occurs in the materials due to process heat affecting the materials during a manufacturing process, which causes degradation of device characteristics such as increase of the gate leakage current and change of flat band voltage. Accordingly, a device formation process applying less heat load on materials of the high-K gate insulating film and the metal gate electrode is required.
For example, U.S. Pat. No. 6,171,910 (Patent Document 1) discloses a damascene gate process technique as a technique of forming a MIS transistor without applying heat load to a high-K gate insulating film and a metal gate electrode.
For example, U.S. Patent Application Publication No. 2006/0157797 (Patent Document 2), Japanese Patent Application Laid-Open Publication No. 2007-073695 (Patent Document 3), and Japanese Patent Application Laid-Open Publication No. 2007-088046 (Patent Document 4) disclose techniques in which source/drain regions are stacked on a substrate, and then, a sidewall film is formed to a dummy gate, and materials of a high-K gate insulating film and a metal gate electrode are buried in a portion obtained by removing the dummy gate. Also, these Patent Documents 2 to 4 also disclose methods of directly forming the gate insulating film on the stacked source/drain regions.
Further, for example, 2003 Symposium on VLSI Technology Digest of Technical Papers, pp. 11 to 12 (Non-Patent Document 1) discloses a technique of employing a recess structure to a channel region of a transistor.